1. Technical Field:
The present invention relates generally to digital clock circuits, and more particularly, to circuits and systems that evaluate clock jitter and duty cycle.
2. Description of the Related Art:
Determining nominal pulse width and jitter of a clock signal is necessary to evaluate the performance of high-speed interface components and interfaces, as well as other circuits having high-frequency clocks. Determining nominal pulse width and jitter of a clock signal is also desirable in many circuits that determine the quality of a received or generated clock and/or circuits that adapt performance in order to accommodate a level of jitter and/or pulse width deviations in a clock signal.
In laboratory environments, high-accuracy laboratory instruments may be used to determine the jitter and/or pulse width of a clock signal via very stable reference clocks and long integration times. However, the challenge of probing a very high frequency clock and/or high-impedance signal is significant, as the effects of the probe must be accounted for in the measurements and probe characteristics can vary over time and the probe compensation model may not be accurate under actual measurement conditions. Further, significant circuit area can be consumed in the impedance-matched and isolated output pads that permit such precision measurements. Such equipment is expensive and it is typically unfeasible to incorporate the equivalent of such instrumentation within production circuits.
Typically, in on-chip measurements a jitter and/or pulse width measurement is performed using a synchronous clock that is generated locally in phase-lock or with a high degree of frequency accuracy with the clock signal being measured. Thus the exact frequency of the clock signal being measured must be known. Alternatively, the amplitude of error or feedback signals of a phase-lock loop (PLL) circuit locked to a clock may be observed to determine the amount of jitter present in a clock signal. Some PLL techniques employ an adjustable delay line that provides for measuring the distribution of clock edge position, but requires a complex circuit and stable reference clock. Clock pulse width may also be determined from an average DC signal level of the clock, but generally not with high accuracy due to low-frequency noise. However, achieving accuracy with any of the above-described PLL techniques when applied to a high-frequency clock typically require a PLL circuit just as costly as the clock source itself and with an inherent stability that is at least an order of magnitude greater.
It is therefore desirable to provide a method and apparatus for determining jitter and pulse width of a clock signal that is low cost, can be at least partially integrated in a production circuit with no probing error and can quickly determine the jitter and pulse width of a clock signal of unknown frequency.